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xicor, inc. 1994, 1995, 1996, 1998 patents pending 7078 1.1 8/9/99 cm 1 characteristics subject to change without notice watchdog timer x5001 cpu supervisor features ? 200ms power on reset delay ? low vcc detection and reset assertion five standard reset threshold voltages adjust low vcc reset threshold voltage using special programming sequence reset signal valid to vcc=1v ? selectable nonvolatile watchdog timer 0.2, 0.6, 1.4 seconds off selection select settings through software ? long battery life with low power consumption <50 m a max standby current, watchdog on <1 m a max standby current, watchdog off ? 2.7v to 5.5v operation ? spi mode 0 interface ? built-in inadvertent write protection power-up/power-down protection circuitry watchdog change latch ? high reliability ? available packages 8-lead tssop 8-lead soic 8 pin pdip description this device combines three popular functions, power on reset, watchdog timer, and supply voltage supervision in one package. this combination lowers system cost, reduces board space requirements, and increases reli- ability. the watchdog timer provides an independent protection mechanism for microcontrollers. during a system failure, the device will respond with a reset signal after a selectable time-out interval. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the users system is protected from low voltage condi- tions by the devices low vcc detection circuitry. when vcc falls below the minimum vcc trip point, the system is reset. reset is asserted until vcc returns to proper operating levels and stabilizes. five industry standard v trip thresholds are available, however, xicors unique circuits allow the thresold to be reprogrammed to meet custom requirements or to ?ne-tune the threshold for applications requiring higher precision. the device utilizes xicors proprietary direct write tm cell for the watchdog timer control bits and the v trip stor- age element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. block diagram data register command decode & control logic si so sck cs /wdi 7036 frm 01 v cc watchdog transition detector reset & watchdog timebase power on/ generation v trip + - reset reset low voltage
x5001 2 pin description figure 1. pin configuration pin (soic/pdip) pin tssop name function 11cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the de- vice will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power up, a high to low transition on cs is required watchdog input. a high to low transition on the wdi pin restarts the watch- dog timer. the absence of a high to low transition within the watchdog time- out period results in reset /reset going active. 22so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb ?rst. 6 9 sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or watchdog bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36 v pe v trip program enable. when v pe is low, the v trip point is ?xed at the last valid programmed level. to readjust the v trip level, requires that the vpe pin be pulled to a high voltage (15-18v). 47 v ss ground 814 v cc supply voltage 7 13 reset reset output . reset is an active low, open drain output which goes active whenever vcc falls below the minimum vcc sense level. it will remain active un- til vcc rises above the minimum vcc sense level for 200ms. reset goes active if the watchdog timer is enabled and cs /wdi remains either high or low longer than the selectable watchdog time-out period. a falling edge of cs /wdi will reset the watchdog timer. reset goes active on power up at 1v and re- mains active for 200ms after the power supply stabilizes. 3-5,10-12 nc no internal connections 8 lead soic/pdip x5001 cs /wdi so 1 2 3 4 reset 8 7 6 5 v cc v ss sck si sck si v ss v cc cs /wdi so 1 2 3 4 8 7 6 5 8 lead tssop x5001 reset v pe v pe
x5001 3 principles of operation power on reset application of power to the x5001 activates a power on reset circuit. this circuit goes active at 1v and pulls the reset /reset pin active. this signal prevents the sys- tem microprocessor from starting to operate with insuf?- cient voltage or prior to stabilization of the oscillator. when vcc exceeds the device v trip value for 200ms (nominal) the circuit releases reset , allowing the processor to begin executing code. low voltage monitoring during operation, the x5001 monitors the v cc level and asserts reset if supply voltage falls below a preset mini- mum v trip . the reset signal prevents the microproces- sor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until vcc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the wdi input. the microprocessor must toggle the cs /wdi pin periodically to prevent a reset signal. the cs /wdi pin must be toggled from high to low prior to the expiration of the watchdog time- out period. the state of two nonvolatile control bits in the watchdog register determine the watchdog timer period. vcc threshold reset procedure the x5001 is shipped with a standard vcc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x5001 threshold may be adjusted. the procedure is described below, and requires the application of a high voltage con- trol signal. setting the v trip voltage this procedure is used to set the v trip to a higher volt- age value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the cur- rent setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold voltage to the vcc pin and tie the w pe pin to the programming voltage v p . then a v trip programming command sequence is sent to the device over the spi interface. this v trip programming sequence consists of pulling cs low, then clocking in data 03h, 00h and 01h. this is followed by bringing cs high then low and clocking in data 02h, 00h, and 01h (in order) and bringing cs high. this initiates the v trip programming sequence. v p is brought low to end the operation. resetting the v trip voltage this procedure is used to set the v trip to a native volt- age level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply greater than 3v to the vcc pin and tie the w pe pin to the programming voltage vp. then a v trip command sequence is sent to the device over the spi interface. this v trip programming sequence consists of pulling cs low, then clocking in data 03h, 00h and 01h. this is followed by bringing cs high then low and clocking in data 02h, 00h, and 03h (in order) and bringing cs high. this initiates the v trip programming sequence. v p is brought low to end the operation.
x5001 4 figure 2. sample v trip reset circuit figure 3. set v trip level sequence (vcc=desired v trip value. ) figure 4. reset v trip level sequence (vcc > 3v. ) 1 2 3 4 8 7 6 5 x5001 v trip adj. v p reset 4.7k si so cs sck uc adjust run 012 3 45678910 sck si cs 20 21 22 23 16 bits 0001h 03h 012 3 45678910 20 21 22 23 16 bits 0001h 02h v pe v pe = 15-18v 012 3 45678910 sck si cs 20 21 22 23 16 bits 0001h 03h 012 3 45678910 20 21 22 23 16 bits 0003h 02h v pe v pe = 15-18v 16 bits
x5001 5 figure 5. vtrip programming sequence vtrip programming apply 5v to vcc decrement vcc reset pin goes active? measured vtrip - desired vtrip done execute sequence reset vtrip set vcc = vcc applied = desired vtrip execute sequence set vtrip new vcc applied = old vcc applied + error (vcc = vcc - 50mv) execute sequence reset vtrip new vcc applied = old vcc applied - error error < 0 error = 0 yes no error > 0
x5001 6 spi interface the device is designed to interface directly with the syn- chronous serial peripheral interface (spi) of many popu- lar microcontroller families. the device monitors the cs /wdi line and asserts reset output if there is no activity within user selctable time-out period. the device also monitors the vcc supply and asserts the reset if vcc falls below a preset minimum (v trip ). the device contains an 8-bit watchdog timer register to control the watchdog time-out period. the cur- rent settings are accessed via the si and so pins. all instructions (table 1) and data are transferred msb ?rst. data input on the si line is latched on the ?rst rising edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. watchdog timer register watchdog timer control bits the watchdog timer control bits, wd 0 and wd 1 , select the watchdog time-out period. these nonvolatile bits are programmed with the set watchdog timer (swdt) instruction. write watchdog register operation changing the watchdog timer register is a two step pro- cess. first, the change must be enabled with by setting the watchdog change latch (see below). this instruction is followed by the set watchdog timer (swdt) instruc- tion, which includes the data to be written (figure 5). data bits 3 and 4 contain the watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be 0 . watchdog change latch the watchdog change latch must be set before a write watchdog timer operation is initiated. the enable watchdog change (ewdc) instruction will set the latch and the disable watchdog change (dwdc) instruction will reset the latch (see figure 2.) this latch is automati- cally reset upon a power-up condition and after the com- pletion of a valid nonvolatile write cycle. read watchdog timer register operation if there is not a nonvolatile write in progress, the read watchdog timer instruction returns the setting of the watchdog timer control bits. the other bits are reserved and will return 0 when read. see figure 3. if a nonvolatile write is in progress, the read watchdog timer register instruction returns a high on so. when the nonvolatile write cycle is completed, a seperate read watchdog timer instruction should be used to determine the current status of the watchdog control bits. reset operation the reset (x5001) output is designed to go low whenever v cc has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time-out limit. the reset output is an open drain output and requires a pull up resistor. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the watchdog change latch is reset. ? the reset signal is active for t purst . data protection the following circuitry has been included to prevent inad- vertent writes: ? a ewdc instruction must be issued to enable a change to the watchdog timeout setting. ?cs must come high at the proper clock count in order to implement the requested changes to the watchdog timeout setting. 7 6543210 000 wd 1 wd 0 000 watchdog control bits watchdog time-out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled
x5001 7 table 1. instruction set de?nition notes: instructions are shown with msb in leftmost position. instructions are transferred msb ?rst. 7038 frm t03 figure 1. read watchdog timer setting figure 2. enable watchdog change/disable watchdog change sequence instruction format instruction name and operation 0000 0110 ewdc: enable watchdog change operation 0000 0100 dwdc: disable watchdog change operation 0000 0001 swdt: set watchdog timer control bits: instruction followed by contents of register: 000(wd 1 ) (wd 0 )000 see watchdog timer settings and figure 3. 0000 0101 rwdt: read watchdog timer control bits 01234567 cs sck si so rwdt instruction ... ... ... w d 0 w d 1 01234567 cs si sck high impedance so instruction (1 byte)
x5001 8 figure 3. write watchdog timer sequence figure 4. read nonvolatile status (option 1) (used to determine end of watchdog timer store operation) figure 5. read nonvolatile status (option 2) (used to determine end of watchdog timer store operation) 0123456789 cs sck si so high impedance instruction 10 11 12 13 14 15 data byte 65 4 3 w d 1 w d 0 01234567 cs sck si so nonvolatile write in progress rwdt instruction so high during 1st bit while in the nonvolatile write cycle 01234567 cs sck si so nonvolatile write in progress rwdt instruction so high during nonvolatile write cycle
x5001 9 d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?ed.) power-up timing capacitance t a = +25c, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. typ. max. i cc1 v cc write current (active) 5ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i sb1 v cc standby current wdt=off 1 a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt=on 50 a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt=on 20 a cs = v cc , v in = v ss or v cc , v cc =3.6v i li input leakage current 0.1 10 a v in = v ss to v cc i lo output leakage current 0.1 10 a v out = v ss to v cc v il (1) input low voltage C0.5 v cc x0.3 v v ih (1) input high voltage v cc x0.7 v cc +0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc < 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc C0.8 v v cc > 3.3v, i oh = C1.0ma v oh2 output high voltage v cc C0.4 v 2v < v cc 3.3v, i oh = C0.4ma v oh3 output high voltage v cc C0.2 v v cc 2v, i oh = C0.25ma v olrs reset output low voltage 0.4 v i ol = 1ma symbol parameter min. max. units t pur (2) power-up to read operation 1ms t puw (2) power-up to write operation 5ms symbol test max. units conditions c out (2) output capacitance (so, reset ) 8pfv out = 0v c in (2) input capacitance (sck, si, cs ) 6pfv in = 0v absolute maximum ratings* temperature under bias ........................C65c to +135c storage temperature .............................C65c to +150c voltage on any pin with respect to v ss ....... C1.0v to +7v d.c. output current ....................................................5ma lead temperature (soldering, 10 seconds)............ 300c recommended operating conditions 7036 frm t07 *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pt= package, temperature temp min. max. commercial 0c +70c voltage option supply voltage limits C1.8 1.8v to 3.6v C2.7 or -2.7a 2.7v to 5.5v C4.5 or -4.5a 4.5v to 5.5v
x5001 10 a.c. characteristics (over recommended operating conditions, unless otherwise speci?ed) data input timing data output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 1.8vC3.6v 2.7vC5.5v symbol parameter min. max. min. max. units f sck clock frequency 0102mhz t cyc cycle time 1000 500 ns t lead cs lead time 400 200 ns t lag cs lag time 400 200 ns t wh clock high time 400 200 ns t wl clock low time 400 200 ns t su data setup time 100 50 ns t h data hold time 100 50 ns t ri (3) input rise time 22s t fi (3) input fall time 22s t cs cs deselect time 250 150 ns t wc (4) write cycle time 10 10 ms 1.8vC3.6v 2.7vC5.5v symbol parameter min. max. min. max. units f sck clock frequency 0102mhz t dis output disable time 400 200 ns t v output valid from clock low 400 200 ns t ho output hold time 00ns t ro (3) output rise time 300 150 ns t fo (3) output fall time 300 150 ns figure 1. equivalent a.c. load circuit a.c. test conditions 3v output 100pf 5v 3.3k w reset 30pf 1.64k w 1.64 k w input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5
x5001 11 figure 1. data output timing figure 2. data input timing sck cs so si msb out msbC1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance figure 1. symbol table
x5001 12 figure 1. power-up and power-down timing reset output timing notes: (5) this parameter is periodically sampled and not 100% tested. pt = package, temperature figure 2. cs vs. reset timing reset output timing symbol parameter min. typ. max. units v trip reset trip point voltage, x5001pt-4.5a reset trip point voltage, x5001pt-4.5 reset trip point voltage, x5001pt-2.7a reset trip point voltage, x5001pt-2.7 reset trip point voltage, x5001pt-1.8 4.50 4.25 2.85 2.55 1.70 4.63 4.38 2.92 2.63 1.75 4.75 4.50 3.00 2.70 1.80 v t purst power-up reset timeout 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 0.1 ns t r (5) v cc rise time 0.1 ns v rvalid reset valid v cc 1v symbol parameter min. typ. max. units t wdo watchdog timeout period, wd 1 = 1, wd 0 = 0 wd 1 = 0, wd 0 = 1 wd 1 = 0, wd 0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 200 300 ms vcc t purst t purst t r t f t rpd reset (x5001) 0 volts v trip v trip cs t cst reset t wdo t rst t wdo t rst
x5001 13 v trip programming timing diagram sck si cs 0001h or 02h vcc ( v trip ) v pe t tsu t thd t vph t vps v p v trip t rp t vpo t pcs 0003h 0001h 03h
x5001 14 v trip programming parameters parameter description min max units t vps v trip program enable voltage setup time 1 m s t vph v trip program enable voltage hold time 1 m s t pcs v trip programming cs inactive time 1 m s t tsu v trip setup time 1 m s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0us t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (vcc applied - v trip ) (programmed at 25 o c.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(vcc applied - v ta1 ) - v trip . programmed at 25 o c.) -25 +25 mv v tr v trip program voltage repeatability (successive program operations. programmed at 25 o c.) -25 +25 mv v tv v trip program variation after programming (0-75 o c). (programmed at 25 o c.) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested.
x5001 15 watchdog timer on (vcc = 5v) watchdog timer on (vcc = 3v) watchdog timer off (vcc = 3v, 5v) C40c 25c 90c temp (c) isb (ua) vcc supply current vs. temperature (i sb )t wdo vs. voltage/temperature (wd1,0=1,1) v trip vs. temperature (programmed at 25c) t wdo vs. voltage/temperature (wd1,0=1,0) t purst vs. temperature t wdo vs. voltage/temperature (wd1,0 0=0,1) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.7 3.1 4.5 90c 25c C40c reset (seconds) voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage temperature vtrip=5v vtrip=3.5v vtrip=2.5v 0.85 0.80 0.75 0.70 0.65 0.60 1.7 4.5 reset (seconds) voltage 3.1 90c 25c C40c 275 270 265 260 255 250 245 240 235 C40 25 90 degrees c 280 time (ms) 90c 25c C40c 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.29 reset (seconds) voltage 1.7 3.1 4.5 14 11 17 15 20 18 0.35 0.55 1.0 0.30
x5001 16 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x5001 17 note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x5001 18 ordering information vcc range vtrip range package operating temperature range part number reset (active low) 4.5-5.5v 4.5.4.75 8 pin pdip 0 o c - 70 o c x5001p-4.5a 8l soic 0 o c - 70 o c x5001s8-4.5a 8l tssop 0 o c - 70 o c X5001V8-4.5a 4.5-5.5v 4.25.4.5 8 pin pdip 0 o c - 70 o c x5001p 8l soic 0 o c - 70 o c x5001s8 8l tssop 0 o c - 70 o c X5001V8 2.7-5.5v 2.85-3.0 8l soic 0 o c - 70 o c x5001s8-2.7a 2.7-5.5v 2.55-2.7 8l soic 0 o c - 70 o c x5001s8-2.7 8l tssop 0 o c - 70 o c X5001V8-2.7
x5001 19 part mark information 8-lead tssop 501ag = 1.8 to 3.6v, 0 to +70c, v trip =1.7-1.8v yww xxxxx 501ah = 1.8 to 3.6v, -40 to +85c, v trip =1.7-1.8v 501f = 2.7 to 5.5v, 0 to +70c, v trip =2.55-2.7v 501g = 2.7 to 5.5v, -40 to +85c, v trip =2.55-2.7v 501 = 4.5 to 5.5v, 0 to +70c, v trip =4.25-4.5v 501i = 4.5 to 5.5v, -40 to +85c, v trip =4.25-4.5v 8-lead soic x5001 yww xx ag = 1.8 to 3.6v, 0 to +70c, v trip =1.7-1.8v ah = 1.8 to 3.6v, -40 to +85c, v trip =1.7-1.8v f = 2.7 to 5.5v, 0 to +70c, v trip =2.55-2.7v g = 2.7 to 5.5v, -40 to +85c, v trip =2.55-2.7v i = 4.5 to 5.5v, -40 to +85c, v trip =4.25-4.5v 501an = 2.7 to 5.5v, 0 to +70c, v trip =2.85-3.0v 501ap = 2.7 to 5.5v, -40 to +85c, v trip =2.85-3.0v 501al = 4.5 to 5.5v, 0 to +70c, v trip =4.5-4.75v 501am = 4.5 to 5.5v, -40 to +85c, v trip =4.5-4.75v an = 2.7 to 5.5v, 0 to +70c, v trip =2.85-3.0v ap = 2.7 to 5.5v, -40 to +85c, v trip =2.85-3.0v al = 4.5 to 5.5v, 0 to +70c, v trip =4.5-4.75v am = 4.5 to 5.5v, -40 to +85c, v trip =4.5-4.75v blank = 4.5 to 5.5v, 0 to +70c, v trip =4.25-4.5v yww = year/work week device is packaged. limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appro- priate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonabl y expected to result in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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